1. EUPHORIA SUPPORT FOR IMPULSEC
- Posted by w108dab Dec 27, 2009
- 1202 views
To All,
I was wonddering if anyone would be interested in helping me to develop a euphoria to ImpulseC compiler or translator? The ImpulseC environment is based on the notion to utilize the C programming language to be translated to VHDL or Verilog for FPGA implementation. I strongly believe that a Euphoria / ImpulseC creation would allow both systems to become more visible within industry
Thank You,
David
2. Re: EUPHORIA SUPPORT FOR IMPULSEC
- Posted by menno Dec 27, 2009
- 1159 views
I donn't think that somebody is waiting for a Euphoria -> VHDL/Verilog . There are better graphical system that will do that . On the other hand , the problem is not VHDL but the synthese tools how handle the real hardware . This is often not a very open software domain . The way they download the bitstreams into a device , was in early time very open , is mostly protectted now . In the years 90 Lattice , AMD , Cypress give there software free to use . The WRAP software was very good , as far as I know its no longer free . Greatings Menno
3. IMPULSEC
- Posted by w108dab Dec 28, 2009
- 1173 views
Yes
You are correct However, there are advantages with developing a scripting language that is designed to work with the ImpulseC model. for example, such as partitioning a design across both hardware and software resources within a FPGA device. The graphical tools i think that you are talking about is environments such as Matlab or simulink. However, these graphical environments cannot develop a design for a hybrid implementation for partitioning a design or algorithm acroos both the hardware and software resources of a FPGA device. Does what i say so far make any sense ??
David
4. Re: IMPULSEC
- Posted by menno Dec 28, 2009
- 1070 views
The graphical tools I was thinging about are those of Aldec (Active-HDL) , Synopsis , Cadenece and Mentor Graphics . I have used the simulators of Aldec and they where good . From design site point of view I dislike most of thim . Because I have know idea why they make a design . They are mostly not optimal . Most of those tool forbid you to make oscilators ( a:=~a ) . I must admid that the design I had done with a mix soft/hardware mostly is done by buttom-up design procedures AND not by a top-down . I read some artical about IMPULS-C but I donn't understand why that should leed to a better FPGA imlementation then doiing that directly in VHDL (or Verilog's RTL) . This because the biggest problem lays in the synthesetools . There is also a possebility that I donn't understand your question . Greatings Menno .
