Re: IMPULSEC
- Posted by menno Dec 28, 2009
- 1068 views
The graphical tools I was thinging about are those of Aldec (Active-HDL) , Synopsis , Cadenece and Mentor Graphics . I have used the simulators of Aldec and they where good . From design site point of view I dislike most of thim . Because I have know idea why they make a design . They are mostly not optimal . Most of those tool forbid you to make oscilators ( a:=~a ) . I must admid that the design I had done with a mix soft/hardware mostly is done by buttom-up design procedures AND not by a top-down . I read some artical about IMPULS-C but I donn't understand why that should leed to a better FPGA imlementation then doiing that directly in VHDL (or Verilog's RTL) . This because the biggest problem lays in the synthesetools . There is also a possebility that I donn't understand your question . Greatings Menno .
