1. CPU Detection
Hi people,
I wrote a little proggie to gather some information about a cpu. The main
thing I want to detect is support for MMX instructions. So I need to
know if this little code properly detects that capability of your cpu. It
should run on all platforms, though I've only tried Linux. Let me know if
it works on others.
Intel Pentiums and better with MMX should report just that.
AMD K6-2's and better should have MMX and 3DNow.
Older chips will probably print "undetermined" or just the vendor string.
If you don't trust this code even a little bit, then I recommend you do
not run it. The listserv has had a problem in the past with someone
posting a trojan horse that erased files on your hard drive. This program
doesn't do anything malicious like that, but I still disclaim
responsibility if it misbehaves on your machine.
-- test_cpuid.ex
include machine.e
integer has_MMX, has_3DNow
sequence vendor_string
procedure test_cpuid()
atom proc, cpuid_result, vend_str
proc = allocate(99)
poke(proc, {
#60, -- 0: pusha
#9C, -- 1: pushf
#31,#F6, -- 2: xor esi, esi
#58, -- 4: pop eax
#89,#C3, -- 5: mov ebx, eax
#35,#00,#00,#20,#00, -- 7: xor eax, #00200000
#50, -- C: push eax
#9D, -- D: popf
#9C, -- E: pushf
#58, -- F: pop eax
#39,#D8, -- 10: cmp eax, ebx
#74,#46, -- 12: jz NO_CPUID
#B8,#00,#00,#00,#00, -- 14: mov eax, 0
#0F,#A2, -- 19: cpuid
#BF,#00,#00,#00,#00, -- 1B: mov edi, vend_str (28)
#89,#1F, -- 20: mov [edi], ebx
#89,#57,#04, -- 22: mov [edi+4], edx
#89,#4F,#08, -- 25: mov [edi+8], ecx
#B8,#01,#00,#00,#00, -- 28: mov eax, 1
#0F,#A2, -- 2D: cpuid
#F7,#C2,#00,#00,#80,#00,-- 2F: test edx, #00800000
#74,#23, -- 35: jz NO_MMX
#83,#CE,#01, -- 37: or esi, 1
#B8,#00,#00,#00,#80, -- 3A: mov eax, #80000000
#0F,#A2, -- 3F: cpuid
#3D,#00,#00,#00,#80, -- 41: cmp eax, #80000000
#76,#12, -- 46: jbe NO_EXTENDEDMSR
#B8,#01,#00,#00,#80, -- 48: mov eax, #80000001
#0F,#A2, -- 4D: cpuid
#F7,#C2,#00,#00,#00,#80,-- 4F: test edx, #80000000
#74,#03, -- 55: jz NO_3DNow
#83,#CE,#02, -- 57: or esi, 2
-- 5A: NO_CPUID:
-- 5A: NO_MMX:
-- 5A: NO_EXTENDEDMSR:
-- 5A: NO_3DNow:
#89,#F0, -- 5A: mov eax, esi
#A2,#00,#00,#00,#00, -- 5C: mov [cpuid_result], al (93)
#61, -- 61: popa
#C3}) -- 62: ret
cpuid_result = allocate(1)
vend_str = allocate(12)
poke(vend_str, "undetermined")
poke4(proc + 28, vend_str)
poke4(proc + 93, cpuid_result)
call(proc)
free(proc)
has_MMX = and_bits(peek(cpuid_result), 1)
has_3DNow = and_bits(peek(cpuid_result), 2) = 2
vendor_string = peek({vend_str, 12})
free(cpuid_result)
free(vend_str)
end procedure
test_cpuid()
puts(1, vendor_string & '\n')
if has_MMX then
puts(1, "This cpu supports MMX instructions\n")
end if
if has_3DNow then
puts(1, "This cpu supports 3DNow instructions\n")
end if
-----------------------------------------------------
The cpuid instruction can report alot more information that is shown here,
like the exact model, cache size, extended instructions support and more.
If you think detecting such things in Euphoria would be useful, tell me
and I would probably hack it in. http://www.sandpile.org/arch/cpuid.htm
has a nice list of all the things you can get using cpuid.
Thanks,
_______ ______ _______ ______
[ _ \[ _ ][ _ _ ][ _ ]
[/| [_] |[/| [_\][/ | | \][/| [_\]
| ___/ | _] | | | _]
[\| [/] [\| [_/] [\| |/] [\| [_/]
[_____] [______] [_____] [______]
xseal at harborside.com ICQ:13466657
http://www.harborside.com/home/x/xseal/euphoria/
2. Re: CPU Detection
AuthenticAMD
This cpu supports MMX instructions
Lucius L. Hilley III
lhilley at cdc.net lucius at ComputerCafeUSA.com
+----------+--------------+--------------+----------+
| Hollow | ICQ: 9638898 | AIM: LLHIII | Computer |
| Horse +--------------+--------------+ Cafe' |
| Software | http://www.cdc.net/~lhilley | USA |
+----------+-------+---------------------+----------+
| http://www.ComputerCafeUSA.com |
+--------------------------------+
3. Re: CPU Detection
Pete,
Your code runs just fine on my PIII-500, and correctly identifies a
GenuineIntel chip with MMX capabilities. It would be nice to see all
the little extras like cache size, etc. I'm sure we could all find some
pretty cool uses for it!
Brian Jackson
4. Re: CPU Detection
Hi Pete
Your program successfully detected my cpu.
It returned:
CyrixInstead
This cpu supports MMX instructions.
Bye
Martin
5. Re: CPU Detection
On Thu, 16 Sep 1999, you wrote:
> Hi people,
>
> I wrote a little proggie to gather some information about a cpu. The main
> thing I want to detect is support for MMX instructions. So I need to
> know if this little code properly detects that capability of your cpu. It
> should run on all platforms, though I've only tried Linux. Let me know if
> it works on others.
On my Linux box this reports correctly:
CyrixInstead
This cpu supports MMX instructions
Irv
6. Re: CPU Detection
Hi Pete,
----- Original Message -----
From: Pete Eberlein <xseal at HARBORSIDE.COM>
To: <EUPHORIA at LISTSERV.MUOHIO.EDU>
Sent: Thursday, September 16, 1999 5:08 AM
Subject: CPU Detection
> Hi people,
>
> I wrote a little proggie to gather some information about a cpu. The main
> thing I want to detect is support for MMX instructions. So I need to
> know if this little code properly detects that capability of your cpu. It
> should run on all platforms, though I've only tried Linux. Let me know if
> it works on others.
AuthenticAMD
This cpu supports MMX instructions
This cpu supports 3DNow instructions
Um.. looks good to me :)
Greg Harris
7. Re: CPU Detection
This message is in MIME format. The first part should be readable text,
while the remaining parts are likely unreadable without MIME-aware tools.
Send mail to mime at docserver.cac.washington.edu for more info.
---1556868092-1180452014-937519645=:27115
Thanks to Andrew, Lucius, Brian, Martin and Irv for reporting the various
results of different cpus. I assume it worked with exw.exe as well as
ex.exe, or did anyone try?
Brian Jackson wrote:
>Your code runs just fine on my PIII-500, and correctly identifies a
>GenuineIntel chip with MMX capabilities. It would be nice to see all
>the little extras like cache size, etc. I'm sure we could all find some
>pretty cool uses for it!
Okay, I've attached the code with *all* the extras:
* cpu family/model/stepping
* FPU/MMX/3DNow detection
* cache sizes
* the controversial serial# on P3's 
* and all I really wanted was to check for MMX...
Rob, you may put it on the contributions page too.
Laters,
_______ ______ _______ ______
[ _ \[ _ ][ _ _ ][ _ ]
[/| [_] |[/| [_\][/ | | \][/| [_\]
| ___/ | _] | | | _]
[\| [/] [\| [_/] [\| |/] [\| [_/]
[_____] [______] [_____] [______]
xseal at harborside.com ICQ:13466657
http://www.harborside.com/home/x/xseal/euphoria/
---1556868092-1180452014-937519645=:27115
9. Re: CPU Detection
GenuineIntel
Intel P2 with on-die L2 cache
This cpu supports Floating-Point instructions
This cpu supports MMX instructions
stepping = 5
code TLB, 4K pages, 4 ways, 32 entries
code TLB, 4M pages, fully, 2 entries
data TLB, 4K pages, 4 ways, 64 entries
code and data L2 cache, 128KB, 4 ways, 32 byte lines
code L1 cache, 16KB, 4 ways, 32 byte lines
data TLB, 4M pages, 4 ways, 8 entries
data L1 cache, 16KB, 4 ways, 32 byte lines
Impressive!!
Greg Phillips
10. Re: CPU Detection
- Posted by JJProg at CYBERBURY.NET
Sep 16, 1999
EU>Thanks to Andrew, Lucius, Brian, Martin and Irv for reporting the various
EU>results of different cpus. I assume it worked with exw.exe as well as
EU>ex.exe, or did anyone try?
EU>Brian Jackson wrote:
EU>>Your code runs just fine on my PIII-500, and correctly identifies a
EU>>GenuineIntel chip with MMX capabilities. It would be nice to see all
EU>>the little extras like cache size, etc. I'm sure we could all find some
EU>>pretty cool uses for it!
EU>Okay, I've attached the code with *all* the extras:
EU> * cpu family/model/stepping
EU> * FPU/MMX/3DNow detection
EU> * cache sizes
EU> * the controversial serial# on P3's
EU> * and all I really wanted was to check for MMX...
EU>Rob, you may put it on the contributions page too.
EU>Laters,
EU> _______ ______ _______ ______
EU>[ _ \[ _ ][ _ _ ][ _ ]
EU>[/| [_] |[/| [_\][/ | | \][/| [_\]
EU> | ___/ | _] | | | _]
EU>[\| [/] [\| [_/] [\| |/] [\| [_/]
EU>[_____] [______] [_____] [______]
EU>xseal at harborside.com ICQ:13466657
Is there any way to detect SSE? Also, are you going to add MMX/3DNow/SSE
instructions to asm.e? That would be really neat (though I currently can
only use MMX, unfortunaty). I've tried using NASM to generate the MMX
opcodes, but it seems to use some different segmentation or something
from Euphoria (I don't know too much about segments, except that they
seem like a pain), and it doesn't work.
Jeffrey Fielding
JJProg at cyberbury.net
http://members.tripod.com/~JJProg/
11. Re: CPU Detection
Jeff asks:
>Is there any way to detect SSE?
Yup, it's bit 25 in EDX from CPUID with EAX = 1
add the variable and the line:
has_SSE = and_bits(EDX, #02000000) != 0
>Also, are you going to add MMX/3DNow/SSE instructions to asm.e?
MMX - yes
3DNow - maybe
SSE - unlikely, but if you can convince me to...
>That would be really neat (though I currently can
>only use MMX, unfortunaty). I've tried using NASM to generate the MMX
>opcodes, but it seems to use some different segmentation or something
>from Euphoria (I don't know too much about segments, except that they
>seem like a pain), and it doesn't work.
>
>Jeffrey Fielding
>JJProg at cyberbury.net
>http://members.tripod.com/~JJProg/
I have an AMD K6-2 3DNow at home which supports MMX and 3DNow, and an Intel
P3 Xeon at work which supports MMX and SSE. Looks like I've got it covered,
now all I have to do is code the instructions into asm.e.
Later,
_______ ______ _______ ______
[ _ \[ _ ][ _ _ ][ _ ]
[/| [_] |[/| [_\][/ | | \][/| [_\]
| ___/ | _] | | | _]
[\| [/] [\| [_/] [\| |/] [\| [_/]
[_____] [______] [_____] [______]
xseal at harborside.com ICQ:13466657
http://www.harborside.com/home/x/xseal/euphoria/
12. Re: CPU Detection
AuthenticAMD
AMD K6-2
This cpu supports Floating-Point instructions
This cpu supports MMX instructions
This cpu supports 3DNow instructions
stepping = 4
AMD-K6(tm) 3D processor
code TLB, 4KB pages, direct mapped, 64 entries
data TLB, 4KB pages, 2-way, 128 entries
code L1 cache, 32KB, 2-way, 32 byte lines
data L1 cache, 32KB, 2-way, 32 byte lines
Good job, Pete! :)
13. Re: CPU Detection
AuthenticAMD
AMD K6 (0.25 um)
This cpu supports Floating-Point instructions
This cpu supports MMX instructions
stepping = 0
AMD-K6tm w/ multimedia extensions
code TLB, 4KB pages, direct mapped, 64 entries
data TLB, 4KB pages, 2-way, 128 entries
code L1 cache, 32KB, 2-way, 32 byte lines
data L1 cache, 32KB, 2-way, 32 byte lines
Also tested using exw.ex Had to put in a wait to
see the results.
while get_key() = 27 do
end while
Now if someone would just fix my [ESC] key :)
Lucius L. Hilley III
lhilley at cdc.net lucius at ComputerCafeUSA.com
+----------+--------------+--------------+----------+
| Hollow | ICQ: 9638898 | AIM: LLHIII | Computer |
| Horse +--------------+--------------+ Cafe' |
| Software | http://www.cdc.net/~lhilley | USA |
+----------+-------+---------------------+----------+
| http://www.ComputerCafeUSA.com |
+--------------------------------+
14. Re: CPU Detection
Pete Eberlein wrote:
> >Also, are you going to add MMX/3DNow/SSE instructions to asm.e?
>
> MMX - yes
> 3DNow - maybe
> SSE - unlikely, but if you can convince me to...
Ah come on, make that 3DNow a yes! Hehe... :)
- Todd Riggins
15. Re: CPU Detection
Pete,
I neglected to mention that your program runs just fine with either ex.exe
or exw.exe. I'm running NT4.0 SP4. Hope that helps!
Thanks,
Brian Jackson
16. Re: CPU Detection
- Posted by M King <boot_me at GEOCITIES.COM>
Feb 18, 2000
-
Last edited Feb 19, 2000
Pete, here is my k-6 for you...I am sorting out email that i missed...of
course I realize you are probably long gone past this project :)
I just started working for that customer support place in Coos Bay,
trouble shooting for an east coast ISP, as trucking has little future in it.
W have moved back to Port Orford, only right downtown this time.
Howsit going?
Monty
AuthenticAMD
AMD K6 (0.30 um)
This cpu supports Floating-Point instructions
This cpu supports MMX instructions
stepping = 2
AMD-K6tm w/ multimedia extensions
code TLB, 4KB pages, direct mapped, 64 entries
data TLB, 4KB pages, 2-way, 128 entries
code L1 cache, 32KB, 2-way, 32 byte lines
data L1 cache, 32KB, 2-way, 32 byte lines
